1. Field of the Invention
The present invention relates to an electrostatic breakdown protection diode incorporated in a semiconductor integrated circuit device.
2. Description of the Related Art
Semiconductor integrated circuit devices have inherent weakness that the devices are easily destroyed when high-voltage static charge is applied to the devices from outside because of the structural feature that micro circuits are formed of thin insulating films having a thickness of a few to a few tens of nm and shallow impurity diffused layers having a thickness of a few hundreds of nm to a few tens of micrometers on a silicon substrate. To protect the circuits from the static charge, protection circuits in which a diode is connected in the backward direction against normal input/output signals are disposed between an input/output terminal (input terminal or output terminal) connected to the outside and power source and ground terminals.
More specifically, a P+N−-type diode which an anode is connected to the input/output terminal and a cathode is connected to the power source terminal is-connected between the input/output terminal and the power source terminal. Furthermore, a P−N+-type diode which a cathode is connected to the input/output terminal and an anode is connected to the ground terminal is connected between the input/output terminal and the ground terminal.
FIGS. 2A and 2B are diagrams illustrating the structure of a traditional electrostatic breakdown protection diode. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view along a line 2B—2B shown in FIG. 2A.
This diode is a typical P+N−-type connected between the input/output terminal and the power source terminal, which has a P-type impurity diffused region 12 of high concentration that is disposed on the front surface of an N-type silicon well region 11 of low concentration to form an anode and an N-type impurity diffused region 13 of high concentration that surrounds the P-type impurity diffused region 12 to form a cathode. A field oxide 14 is formed on the surfaces of a separation area for separating the P-type impurity diffused region 12 from the N-type impurity diffused region 13 and the N-type silicon well region 11 extend to outside of the N-type impurity diffused region 13. Moreover, an interlayer dielectric 15 covers the surfaces of the impurity diffused regions 12 and 13 and the field oxide 14. Metal interconnect layers 16 and 17 for connecting the anode to the input/output terminal and the cathode to the power source terminal, respectively, are formed on the interlayer dielectric 15.
The metal interconnect layer 16 has an anode part 16a corresponding to the P-type impurity diffused region 12 and formed smaller than that and an interconnect part 16b for connecting the anode part 16a to the input/output terminal. Furthermore, connecting metals 16c filled in a plurality of connecting holes disposed in the interlayer dielectric 15 connect between the anode part 16a and the P-type impurity diffused region 12.
The metal interconnect layer 17 has a belt-shaped cathode part 17a corresponding to the N-type impurity diffused region 13 and formed smaller than that and an interconnect part 17b for connecting the cathode part 17a to the power source terminal. However, a part of the cathode part 17a is cut out for avoiding intersecting with the interconnect part 16b of the metal layer 16. In addition, connecting metals 17c filled in a plurality of connecting holes disposed in the interlayer dielectric 15 connect between the cathode part 17a and the N-type impurity diffused region 13. Furthermore, an insulating film 18 is formed on the metal interconnect layers 16 and 17, and an interconnect layer, not shown, is formed thereon.
In addition, a typical P−N+-type diode connected between the input/output terminal and the ground terminal has a reverse conductive type of semiconductor having the same structure.
The provision of this electrostatic breakdown protection diode allows static surges to be released on the power source terminal side through the P+N−-type diode in the forward direction when positive static charge is applied to the input/output terminal. Moreover, static surges are released on the ground terminal side through the P−N+-type diode in the forward direction when negative static charge is applied to the input/output terminal. Accordingly, static charge is prevented from entering the inside and internal circuits are protected from electrostatic breakdown.
Patent document JP-A-8-316421
Non-patent document EOS/EDS SYMPOSIUM (1997), S. Voldman et al. Dynamic Threshold Body- and Gate-Coupled SOIESD Protection circuits pp. 210–220